We are looking for highly motivated candidates to work on our projects

PhD positions below

contact : nick.barrett@cea.fr

Title : Multi-level functionality in ferroelectric, hafnia-based thin films for edge logic and memory

The transition to a more attractive, greener and agile economy, providing the very highest quality of life and safety for citizens is a pivotal moment for today’s computing technology. At the heart of this challenge are the technology developments for the transition to a data-centric society.

This generates an immense amount of information to be rapidly processed, analysed and interpreted, enabling autonomous decision-making and, combined with the inventions of powerful computing engines (such as GPUs), has enabled starting from 2010 the deployment of Artificial intelligence (AI) in real applications.

With the rise of the Internet-of-Things (IoT), a huge market for smart edge-devices is foreseen requiring more local storage, computational capacity and intelligence. However, the hardware faces major challenges [Vianello2019]: they are power hungry, expensive (cloud and data-centres), suffer from high leakage power (CMOS volatility), consume a high silicon area (6T SRAM cell per synapse) with memory distributed among many processors (neurons) on a single chip, off-chip memory (data movement) which burns power and taxes bandwidth. When moving data from the edge to the cloud, the situation becomes even worse. It is hard to handle the massively distributed quantity of data using the pure cloud-computing model.

To cope with the requirements of edge AI, new architectures have to be explored in the light of new emerging devices technologies. The Ferro4EdgeAI project aims to develop and demonstrate from 1000X to 2500X energy efficiency gain with respect to cloud based CMOS for intelligent edge processors based on ferroelectric technology and the computation-in-memory paradigm.

The unique characteristics of FE technology [Silva2023] will be explored in the light of the targeted applications. The project focuses on innovation all along the value chain from materials, physics concepts, device architecture, integration technologies and accelerators in a holistic approach.

The primary objective of the PhD thesis is the optimization of HfO2-based ferroelectric materials for multilevel functionality suitable for AI applications by investigating the trade-off in memory window, film thickness & stability of the ferroelectric state. We require a FE film which offers the possibility for a large memory window (large remanent polarization), able to retain the set polarization states.

Low power consumption will be achieved by reducing the switching voltage of the FE thin film which varies with the film thickness, however, as film thickness is reduced, depolarizing effects become more pronounced, which lead to loss of the polarization state and are related to dead layers at the interfaces. Process parameters including Hf content, nanostructuring and annealing conditions will be investigated as will the role of electrodes on depolarizing dead layers.

The device technology at the heart of Ferro4EdgeAI is the FeFET-2 in which a ferroelectric capacitor is added in series with the gate stack of a conventional CMOS transistor (Figure). Conceptually this combines the simplicity and endurance/retention characteristics of the FeRAM with the plasticity and quasi-analogue response of the FeFET, without the adverse effects of charge trapping on endurance, retention, imprint and drift.

     I-V (top left) characteristic of a simple FeFET showing the quasi-analog conductance response as a function of gate voltage [Mulaosmanovic2018]. (top right) FeFET-2 with BEoL FE capacitor in series with the MIS gate stack. Multi-level polarization states shown bottom right are obtained by partial switching using appropriate pulse schemes with respect to the poly-domain structure while avoiding the charge trapping inherent to the FE/channel interface of the simple FeFET. (bottom left) back end of the line FeCAP integrated onto the gate of a standard 130 nm CMOS transistor at CEA LETI.

The thesis work will use piezo-response force microscopy (PFM) for characterizing ferroelectricity in thin films with dominant leakage contributions, photoemission spectroscopy to quantify internal fields, interfacial layer chemistry, band line-ups and defect distributions and concentrations in ferroelectric capacitors (FECAPs).

Electrode materials, ALD electrode deposition, interlayers and annealing conditions will be investigated as parameters to control the interface quality. The influence of cycling and applied bias on polarization switching will be investigated using lab- and synchrotron-based photoemission spectroscopy, including on structured devices with sizes comparable to within the array. This will aid understanding of material behaviour within devices and arrays. Switching kinetics of films with different process parameters and switching voltages will be analysed via time-resolved X-ray photoemission spectroscopy (XPS, PEEM) with a time-resolved detector funded by the project to characterize ML switching.

Extensive use of synchrotron radiation is foreseen for the operando experiments. Samples will be supplied by NaMLab (Dresden) and the CEA LETI (Grenoble) who will also provide the integration. Device reliability will be assessed in collaboration with industrialists (ST Microelectronics and Ferroelectric Memory Company).

CV to nick.barrett@cea.fr before 31st March 2024

[Silva2023] J.P.B. Silva et al, Roadmap on ferroelectric hafnia-and zirconia-based materials and devices APL Mater. 11, 089201 (2023)

[Vianello2019] Vianello, E., L. Perniola, and B. De Salvo. Emerging memory technologies for neuromorphic hardware Advances in Non-Volatile Memory and Storage Technology. Woodhead Publishing 585 (2019)

[Mulaosmanovic2018] H. Mulaosmanovic et al., Accumulative Polarization Reversal in Nanoscale Ferroelectric Transistors ACS Appl. Mater. Interfaces 10, 23997 (2018)